To integrate a semiconductor component into an electronic circuit, the component must be packaged. FIG. 1 shows the cross-section of a typical, multi-chip package 5, which includes substrate 6, semiconductor components 7, and molded housing 8. It should be noted that semiconductor components are interconnected inside the package and to external connectors (not shown) by connectors such as bond wires 9A and in some cases conductive clips, e.g. 9B.
Such semiconductors add to the overall resistance and inductance of the package, and cause undesirable effects such as ringing.
Furthermore, if the package contains heat generating components, in a conventional package such as package 5, a heatsink (not shown) may be thermally coupled to substrate 6 to dissipate the generated heat. The size of the heatsink typically depends on the amount of heat generated. Thus, a large amount of heat would require a larger heatsink. Therefore, heat generation has a bearing on the size of the package.
U.S. Pat. No. 7,045,884, which is assigned to the assignee of the present invention disclosed a package which overcomes the drawbacks of the prior art as set forth above. Referring to FIG. 2, semiconductor package 10 according to U.S. Pat. No. 7,045,884 includes first circuit board 12, and second circuit board 14 which is assembled over first circuit board 12. Circuit boards 12, 14 are of the thermally conductive variety such as insulated metal substrate (IMS), or Direct-bonded copper (DBC). Such circuit boards include a thermally conductive, but electrically insulating body which can have conductive patterns formed over at least one of its surfaces. In the one disclosed embodiment, first circuit board 12 includes a plurality of external connectors 16 which serve as input and output connectors to the elements disposed between first circuit board 12 and second circuit board 14.
Referring next to FIG. 3, semiconductor package 10 includes a plurality of power MOSFETs T1, T2, T3, T4, T5, T6 which are interconnected to form three parallel-connected half-bridge circuits, each for driving a respective phase of a three-phase motor.
As is well known in the art, each half-bridge circuit includes a high side MOSFET, T3, T2, T1 and a low side MOSFET T4, T5, T6. When power MOSFETs are used to form half-bridge circuits, the source contact of the high side MOSFET, e.g. T1, is series connected to the drain contact of the low side MOSFET e.g. T6, while the drain contact of the high side MOSFET is connected to the input power V+ and the source contact of the low side MOSFET is connected to the ground G. Referring to FIG. 3, in the first embodiment of the present invention MOSFET T3, forms a half-bridge with MOSFET T4, MOSFET T2forms a half-bridge with MOSFET T5, and MOSFET T1 forms a half-bridge with MOSFET T6. As is well known the output of each half-bridge circuit A, B, C is taken from the connection point of its high side MOSFET to its respective low side MOSFET as shown by FIG. 3. To operate each MOSFET T1, T2, T3, T4, T5, T6, a gate signal is sent by a control circuit (not shown) through a respective gate connection G1, G2, G3, G4, G5, G6.
Referring now to FIG. 4, first circuit board 12 includes a plurality of source conductive pads 18T1, 18T2, 18T3 for receiving source contacts of high side MOSFETS T1, T2, T3, respectively, and drain conductive pads 20T6, 20T5, 20T4 for receiving the drain contacts of low side MOSFETs T6, T5, T4, respectively. Each conductive pad is an area on a conductive track which has been exposed through an opening in a solder passivation layer formed on the conductive track. The conductive track is itself disposed on the thermally conductive body of a circuit board 12, 14. Specifically, each conductive track is a layer of conductive material, such as copper or aluminum, which is patterned to a desired configuration. Conductive tracks are covered with solder passivation material, and openings are formed in the solder passivation material to expose portions of the conductive tracks to serve as conductive pads.
Source conductive pad 18T1 is connected electrically through a conductive trace 22 on circuit board 12 to conductive pad 20T6, and then connected to external connector 16A through another conductive trace 22 on circuit board 12. Each conductive trace 22 is essentially a portion of the conductive track which electrically connects conductive pads together or to an external connection. Specifically, for example, as will be shown, source conductive pad 18T1, drain conductive pad 20T2, and traces 22, and external connector 16A form a conductive track that provides an output connection for the half-bridge circuit that is formed by MOSFETs T1 and T6.
Conductive pads 18T2, and 18T3 are similarly connected to conductive pads 20T5 and 20T4 and then to external connectors 16B and 16C in a similar manner. As a result, source contacts of high side MOSFETs T1, T2, T3 are electrically connected to drain contacts of respective low side MOSFETs T6, T5, T4 and then connected to external connectors 16A, 16B, 16C, which serve as output connections for each half-bridge circuit without using any wirebonds.
First circuit board 12 also includes gate conductive pads 24T1, 24T2, 24T3 each for receiving a respective gate contact of high side MOSFETs T1, T2, T3. Gate conductive pad 24T1 is connected via a trace 22 to external connector 16G1, which serves as the gate connection for receiving a gate signal for high side MOSFET T1. Similarly, gate pads 24T2 and 24T3 are connected to output connectors 16G2 and 16G3 respectively via traces 22. Connectors 16G2, 16G3 serve as gate connections for high side MOSFETs T2, T3.
Referring now to FIG. 5, second circuit board 14 includes drain conductive pads 20T1, 20T2, 20T3 for receiving drain contacts of high side MOSFETs T1, T2, T3. Second circuit board 14 also includes interconnect conductive pads 28V+ and 28Vground. Drain conductive pads 20T1, 20T2, 20T3 are formed on the same conductive trace as interconnect conductive pads 28V+. Interconnect pads 28V+ are electrically connectable to interconnect pad 29V+ on first circuit board 12, which is electrically connected to external connector 16V+ via a trace 22. As a result drain contacts of high side MOSFET T1, T2, T3 will be connected electrically to external connector 16V+. External connector 16V+ in the first embodiment of the present invention serves as the connection to the input power V+, when second circuit board 14 is disposed over first circuit board 12.
Second circuit board 14 also includes gate conductive pads 24T4, 24T5, 24T6 for receiving gate contacts of low side MOSFETs T4, T5, T6. Each gate conductive pad 24T4, 24T5, 24T6 is electrically connected to gate interconnect pads 28G4, 28G5, 28G6 via a respective trace 22. Each gate interconnect pad 28G4, 28G5, 28G6 is then connected to a corresponding gate interconnect pad 29G4, 29G5, 29G6 on first circuit board 12, and thereby electrically connected via a respective trace 22 to a corresponding gate connector 16G4, 16G5, 16G6.
Also disposed on second circuit board 14 are source conductive pads 18T4, 18T5, 18T6, and ground interconnect pads 28ground. Source conductive pads 18T4, 18T5, 18T6 and ground interconnect pads 28ground are formed on a common conductive track and, therefore, are electrically connected together. Ground interconnect pads 28ground on second circuit board 14 are connected to corresponding ground interconnect pads 29ground on first circuit board 12, which are in turn connected via a common trace 32 to external ground connector 16ground. As a result, source contacts of low side MOSFETs T4, T5, T6 are connectable to a ground connection via external connector 16ground.
Referring now to FIGS. 6 and 7, source contact, e.g. ST1, of each high side MOSFET T1, T2, T3 is electrically connected to a corresponding source conductive pad 18T1, 18T2, 18T3, and each gate contact, e.g. GT1, of each high side MOSFET T1, T2, T3 is electrically connected to a corresponding gate conductive pad 24T1, 24T2, 24T3. Also, each drain contact, e.g. DT6, of each low side MOSFET T4, T5, T6 is electrically connected to its corresponding drain conductive pad, e.g. 20T6, on first circuit board 12. Electrical connection in each case is made by a layer of conductive adhesive 33 such as solder or conductive epoxy. It should be noted that source contact and the gate contact of each MOSFET are exposed through a solder passivation 19 (shown by crossing lines in FIG. 6) layer which prevents the solder (or any other conductive adhesive) from shorting the gate contact to the source contact.
Referring now specifically to FIG. 7, second circuit board 14 is assembled opposite first circuit board 12 such that drain contact, e.g. DT1 of each high side MOSFET T1, T2, T3 is electrically connected via a layer of conductive adhesive 33 to its corresponding drain conductive pad, e.g. 20T1, on second circuit board 14. Similarly, source contact, e.g. ST6, of each low side MOSFET T4, T5, T6 is electrically connected via a layer of conductive adhesive 33 to its corresponding source conductive pad, e.g. 18T6 on second circuit board 14, and gate contact, e.g. GT6, of each low side MOSFET, T4, T5, T6, is electrically connected to its corresponding gate conductive pad, e.g. 24T6, via a layer of conductive adhesive 33.
Also shown in FIG. 7, is interconnect 35 which electrically connects ground conductive pad 29ground on first circuit board 12 to ground conductive pad 28ground on second circuit board 14. Interconnect 35 is connected to each conductive pad via a layer of conductive adhesive 33. Interconnect 35 may be any conductive body such as a copper slug.
FIG. 7 shows that low side MOSFET T6, high side MOSFET T1 and interconnect 35 are connected between first circuit board 12 and second circuit board 14. The remaining high side MOSFETs T2, T3 and low side MOSFETs T4, T5 are connected in the same manner as that of high side MOSFET T1 and low side MOSFET T6. Furthermore, interconnects are used to connect internal gate conductive pads 28G4, 28G5, 28G6 to internal conductive pads 29G4, 29G5, 29G6, and internal conductive pads 28V+ to conductive pads 29V+ in the same manner as described for interconnect 35 above.
Referring now to FIG. 8, once second circuit board 14 is assembled over first circuit board 12, an epoxy underfilling 37 is provided in the spaces between first circuit board 12 and second circuit board 14. The purpose of epoxy underfilling 37 is to protect MOSFETs from environmental conditions such as moisture. As shown by FIG. 8, a heatsink 40 may be thermally coupled to second circuit board 14 to assist in heat dissipation. Heatsink 40 may also be coupled to first circuit board 12 without deviating from the present invention.
Each circuit board 12, 14 may receive a heatsink to effect double-sided cooling. Advantageously, because of double-sided cooling, smaller heatsinks can be used (instead of one large heatsink) thereby reducing the overall size of the package.
Referring now to FIGS. 9A-9D, semiconductor package 10 is manufactured according to the following process. First, solder paste (shown by slanted lines) or some other conductive adhesive is printed on the conductive pads on first circuit board 12. Next, as illustrated by FIG. 9B, high side MOSFETs T1, T2, T3 and low side MOSFETs T4, T5, T6 are placed on their respective positions on first circuit board 12. Thereafter, as illustrated by FIG. 9C, solder paste (shown by slanted lines) or some other conductive adhesive is printed on the conductive pads on second circuit board 14, and, as shown by FIG. 9D, second circuit board 14 is placed over first circuit and then the entire structure is heated to cause the solder paste to be reflown. Thereafter, epoxy is disposed to fill the space between first circuit board 12 and second circuit board 14.
A plurality of first circuit boards 12 may be linked together to form a large panel and MOSFETs T1, T2, T3, T4, T5, T6 and second circuit boards 14 may be placed by a pick-and-place machine. Then, first circuit boards 12 are cut from the large panel to form individual packages after epoxy underfilling has been applied.
A multi-chip package according to the present invention includes several improvements to the package described above with reference to FIG. 1-9.
A package according to the present invention, for example, includes a metallic body extending over preferably the entire free surface of one of the two circuit boards. Furthermore, a package according to the present invention includes at least one external connector which is raised to be coplanar with the metallic body. The external connector may be a copper slug which is electrically connected to a respective conductive track on one of the circuit boards. In one preferred embodiment a package according to the present invention includes elements of only a single half bridge.
A package according to the present invention may further include a dielectric underfilling disposed between the circuit boards and around the semiconductor devices disposed therebetween.
To optimize the performance of a package according to the present invention at least one of the semiconductor devices contained therein may be rectangular (rather than square) with a long and thin aspect ratio in order to
a) minimize adverse thermal characteristics;
b) increase switching speed;
c) max out the solderable area to further improved thermal performance.
A package according to the present invention may be further improved by using a monolithic integrated MOSFET and schottky component, instead of a packaged device containing a discreet MOSFET and a discreet schottky.
Other features and advantages of the present invention will become apparent from the following description of the invention which refers to the accompanying drawings.